SOC RTL Integration

IP Development

Synthesis and STA

Low Power Techniques

LEC Formal Equivalence

Design Quality Checks

Lint, Constraints, CDC, VDC,

Low Power checks

RTL and Netlist Power Roll ups

Curation

Automation Scripts

Floorplanning

Power Planning

Clock Tree Synthesis

Place and Route

Timing Closure

Signal Integrity

RC Extraction

DRC, LVS

IR/EM

ECO (Timing/Functional) implementation

Sign-Off and Tapeout

ESD/Antenna checks

SOC/IP Functional verification

Testbench Development in System Verilog in UVM methodology

Assertion based Verification

Metrics Collection and Coverage closure

Low Power Verification

Hardware/Software co-verification - Emulation, System prototyping

Processor, Multimedia chip Verification

Gate level Simulations - Unit delay and SDF back-annotation

Scan Insertion

Scan Compression

Scan Coverage

Memory BIST

ATPG

JTAG

Scan Timing

SOC/IP/sub-system DFX verification

Boundary Scan, LBIST, MBIST, ATPG, Loop Backs